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(R)
X5043, X5045
4K, 512 x 8 Bit
Data Sheet September 16, 2005 FN8126.1
CPU Supervisor with 4K SPI EEPROM
These devices combine four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor executes code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device's low VCC detection circuitry protects the user's system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Four industry standard VTRIP thresholds are available, however, Intersil's unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. The memory portion of the device is a CMOS Serial EEPROM array with Intersil's block lock protection. The array is internally organized as 512 x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Intersil's proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.
Features
* Low VCC Detection and Reset Assertion - Four standard reset threshold voltages 4.63V, 4.38V, 2.93V, 2.63V - Re-program low VCC reset threshold voltage using special programming sequence. - Reset signal valid to VCC = 1V * Selectable Time Out Watchdog Timer * Long Battery Life with Low Power Consumption - <50A max standby current, watchdog on - <10A max standby current, watchdog off * 4Kbits of EEPROM-1M Write Cycle Endurance * Save Critical Data with Block LockTM Memory - Protect 1/4, 1/2, all or none of EEPROM array * Built-in Inadvertent Write Protection - Write enable latch - Write protect pin * SPI Interface - 3.3MHz Clock Rate * Minimize Programming Time - 16-byte page write mode - 5ms write cycle time (typical) * Available Packages - 8 Ld MSOP, 8 Ld SOIC, 8 Ld PDIP - 14 Ld TSSOP * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Communications Equipment - Routers, Hubs, Switches - Set Top Boxes * Industrial Systems - Process Control - Intelligent Instrumentation * Computer Systems - Desktop Computers - Network Servers * Battery Powered Equipment
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X5043, X5045 Typical Application
2.7-5.0V
VCC
VCC
uC
X5043
RESET CS SCK SI SO WP VSS
10K
RESET SPI
VSS
Block Diagram
POR and Low Voltage Reset Generation Reset & Watchdog Timebase Watchdog Timer Reset RESET (X5043) RESET (X5045)
VCC
VTRIP
+
X5043, X5045 STANDARD VTRIP LEVEL Watchdog Transition Detector 4.63V (+/-2.5%) 4.38V (+/-2.5%) 2.93V (+/-2.5%) 2.63V (+/-2.5%) SUFFIX -4.5A -4.5 -2.7A -2.7
CS/WDI
SI SO SCK WP Command Decode & Control Logic Protect Logic
Status Register EEPROM Array 4Kbits
See "Ordering Information" on page 3. for more details For Custom Settings, call Intersil.
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FN8126.1 September 16, 2005
X5043, X5045 Ordering Information
PART NUMBER RESET (ACTIVE LOW) X5043P-4.5A X5043PZ-4.5A (Note) X5043PI-4.5A X5043PIZ-4.5A (Note) X5043S8-4.5A X5043S8Z-4.5A (Note) X5043S8I-4.5A* X5043S8IZ-4.5A* (Note) X5043M8-4.5A X5043M8Z-4.5A (Note) X5043M8I-4.5A* X5043M8IZ-4.5A (Note) X5043V14I-4.5A X5043P X5043PZ (Note) X5043PI X5043PIZ (Note) X5043ST1 X5043ST2 X5043S8* X5043S8Z* (Note) X5043S8I* X5043S8IZ* (Note) X5043SM* X5043M8 X5043M8Z (Note) X5043M8I X5043M8IZ (Note) X5043V X5043V14I AEO DBN AEP DBJ X5043 X5043 Z X5043 I X5043 Z I X5043P X5043P Z X5043P I X5043P Z I X5043 AL PART MARKING PART NUMBER RESET (ACTIVE HIGH) X5045P-4.5A X5045PZ-4.5A (Note) X5045PI-4.5A X5045PIZ-4.5A (Note) X5045P Z AM X5045S8-4.5A X5045 AL X5045 Z AL X5045 AM X5045 Z AM AEV DCA AEW DBX X5043 Z AL X5045S8Z-4.5A (Note) X5043 AM X5045S8I-4.5A* X5043 Z AM X5045S8IZ-4.5A* (Note) AEM DBS AEN DBM X5045M8-4.5A X5045M8Z-4.5A (Note) X5045M8I-4.5A X5045M8IZ-4.5A (Note) X5045V14I-4.5A X5045P X5045PZ (Note) X5045PI X5045PIZ (Note) X5045S8* X5045S8Z* (Note) X5045S8I* X5045S8IZ* (Note) X5045SMT1 X5045M8 X5045M8Z (Note) X5045M8I X5045M8IZ (Note) X5045V14I AEX DBY AEY DBT X5045P X5045P Z X5045P I X5045P Z I X5045 X5045 Z X5045 I X5045 Z I 4.25-4.5 PART MARKING VCC RANGE 4.5-5.5V VTRIP RANGE 4.5-4.75 TEMP RANGE (C) 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 -40 to 85 PACKAGE 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 14 Ld TSSOP 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC Tape and Reel 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC Tape and Reel 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 14 Ld TSSOP 14 Ld TSSOP
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X5043, X5045 Ordering Information (Continued)
PART NUMBER RESET (ACTIVE LOW) X5043P-2.7A X5043PZ-2.7A (Note) X5043PI-2.7A X5043S8-2.7A* X5043S8Z-2.7A* (Note) X5043S8I-2.7A* X5043S8IZ-2.7A* (Note) X5043M8-2.7A* X5043M8Z-2.7A (Note) X5043M8I-2.7A* X5043M8IZ-2.7A* (Note) X5043V14I-2.7A X5043P-2.7 X5043PZ-2.7 (Note) X5043PI-2.7 X5043PIZ-2.7 (Note) X5043S8-2.7* X5043S8Z-2.7* (Note) X5043S8I-2.7* X5043S8IZ-2.7* (Note) X5043M8-2.7 X5043M8Z-2.7 (Note) X5043M8I-2.7* X5043M8IZ-2.7* (Note) X5043V14I-2.7 X5043P F X5043P G X5043 F X5043 Z F X5043 G X5043 Z G AES DBP AET DBK X5043V G PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART MARKING X5045P AN X5045P Z AN X5045P AP X5045P Z AP X5045 AN X5045 Z AN X5045 AP X5045 Z AP AEZ DCA AFA DBW VCC RANGE 2.7-5.5V VTRIP RANGE 2.85-3.0 TEMP RANGE (C) 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 -40 to 85 X5045P F X5045P Z F X5045P G X5045P Z G 2.55-2.7 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 -40 to 85 X5045 F X5045 Z F X5045 G X5045 Z G AFB DBZ AFC DBU X5045V G 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 -40 to 85 PACKAGE 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 14 Ld TSSOP 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld PDIP 8 Ld PDIP (pb-free) 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 14 Ld TSSOP
X5043P AN X5045P-2.7A X5043P Z AN X5045PZ-2.7A (Note) X5043P AP X5043 AN X5045PI-2.7A X5045S8-2.7A
X5043PIZ-2.7A (Note) X5043P Z AP X5045PIZ-2.7A (Note) X5043 Z AN X5045S8Z-2.7A (Note) X5043 AP X5045S8I-2.7A X5043 Z AP X5045S8IZ-2.7A (Note) AEQ DBR AER DBL X5045M8-2.7A X5045M8Z-2.7A (Note) X5045M8I-2.7A X5045M8IZ-2.7A (Note) X5045V14I-2.7A X5045P-2.7 X5045PI-2.7 X5045S-2.7* X5045SI-2.7* X5045S8-2.7* X5045S8Z-2.7* (Note) X5045S8I-2.7* X5045S8IZ-2.7* (Note) X5045M8-2.7 X5045M8Z-2.7 (Note) X5045M8I-2.7 X5045M8IZ-2.7* (Note) X5045V14I-2.7 X5043P Z F X5045PZ-2.7 (Note) X5043P Z G X5045PIZ-2.7 (Note)
*Add "-T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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X5043, X5045 Pin Configuration
8 Ld SOIC/PDIP/MSOP CS/WDI SO WP VSS 1 2 3 4 8 7 X5043, X5045 6 5 VCC RESET/RESET SCK SI
cycle has already been initiated, WP going low will have no affect on a write.
Reset (RESET, RESET)
X5043, X5045, RESET/RESET is an active low/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET also goes active if the Watchdog timer is enabled and CS remains either high or low longer than the Watchdog time out period. A falling edge of CS will reset the watchdog timer.
14 Ld TSSOP CS SO NC NC NC WP VSS 1 2 3 4 5 6 7 14 13 12 X5043, X5045 11 10 9 8 VCC RESET/RESET NC NC NC SCK SI
Pin Names
SYMBOL CS/WDI SO SI SCK WP DESCRIPTION Chip Select Input Serial Output Serial Input Serial Clock Input Write Protect Input Ground Supply Voltage Reset Output
Pin Descriptions
Serial Output (SO)
SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock.
VSS VCC RESET/RESET
Principles of Operation
Power-on Reset
Application of power to the X5043, X5045 activate a Poweron Reset Circuit. This circuit pulls the RESET/RESET pin active. RESET/RESET prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When VCC exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET/RESET, allowing the processor to begin executing code.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin is latched on the rising edge of the clock input, while data on the SO pin changes after the falling edge of the clock input.
Low Voltage Monitoring
During operation, the X5043, X5045 monitor the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms.
Chip Select (CS/WDI)
When CS is high, the X5043, X5045 are deselected and the SO output pin is at high impedance and, unless an internal write operation is underway, the X5043, X5045 will be in the standby power mode. CS low enables the X5043, X5045, placing it in the active power mode. It should be noted that after power-up, a high to low transition on CS is required prior to the start of any operation.
Watchdog Timer
The Watchdog Timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS/WDI pin periodically to prevent an active RESET/RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two nonvolatile control bits in the Status Register determines the watchdog timer period. The microprocessor can change these watchdog bits. With
FN8126.1 September 16, 2005
Write Protect (WP)
When WP is low, nonvolatile writes to the X5043, X5045 are disabled, but the part otherwise functions normally. When WP is held high, all functions, including non volatile writes operate normally. WP going low while CS is still low will interrupt a write to the X5043, X5045. If the internal write
5
X5043, X5045
no microprocessor action, the watchdog timer control bits remain unchanged, even during total power failure. address 03h. CS going HIGH on the write operation initiates the VTRIP programming sequence. Bring WP LOW to complete the operation. Note: This operation also writes 00h to array address 03h.
VCC Threshold Reset Procedure
The X5043, X5045 are shipped with a standard VCC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X5043, X5045 threshold may be adjusted. The procedure is described below, and uses the application of a high voltage control signal.
Setting the VTRIP Voltage
This procedure is used to set the VTRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V, this procedure will directly make the change. If the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value. To set the new VTRIP voltage, apply the desired VTRIP threshold voltage to the VCC pin and tie the WP pin to the programming voltage VP. Then send a WREN command, followed by a write of Data 00h to address 01h. CS going HIGH on the write operation initiates the VTRIP programming sequence. Bring WP LOW to complete the operation. Note: This operation also writes 00h to array address 01h.
Resetting the VTRIP Voltage
This procedure is used to set the VTRIP to a "native" voltage level. For example, if the current VTRIP is 4.4V and the new VTRIP must be 4.0V, then the VTRIP must be reset. When VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to set the voltage to a lower value. To reset the VTRIP voltage, apply at least 3V to the VCC pin and tie the WP pin to the programming voltage VP. Then send a WREN command, followed by a write of Data 00h to
WP
VP = 15-18V
CS 01234567 SCK 8 Bits SI 06h WREN 02h Write 01h Address 00h Data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIGURE 1. SET VTRIP LEVEL SEQUENCE (VCC = DESIRED VTRIP VALUE.)
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WP
VP = 15-18V
CS 01234567 SCK 8 Bits SI 06h WREN 02h Write 03h Address 00h Data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIGURE 2. RESET VTRIP LEVEL SEQUENCE (VCC > 3V. WP = 15-18V)
4.7K VP Adjust VTRIP Adj. 1 2 3 4 X5043 X5045 8 7 6 5 RESET C
SCK SI SO CS
Run
FIGURE 3. SAMPLE VTRIP RESET CIRCUIT
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SPI Serial Memory
VTRIP Programming
Execute Reset VTRIP Sequence
The memory portion of the device is a CMOS Serial EEPROM array with Intersil's block lock protection. The array is internally organized as 512 x 8 bits. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Intersil's proprietary Direct WriteTM cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years.
New VCC Applied = Old VCC Applied - Error
Set VCC = VCC Applied = Desired VTRIP New VCC Applied = Old VCC Applied - Error
Execute Set VTRIP Sequence Apply 5V to VCC
The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. The device contains an 8-bit instruction register that controls the operation of the device. The instruction code is written to the device via the SI input. There are two write operations that requires only the instruction byte. There are two read operations that use the instruction byte to initiate the output of data. The remainder of the operations require an instruction byte, an 8-bit address, then data bytes. All instruction, address and data bits are clocked by the SCK input. All instructions (Table 1), addresses and data are transferred MSB first.
Execute Reset VTRIP Sequence
Decrement VCC (VCC = VCC-10mV)
NO
RESET pin goes active? YES Measured VTRIP -Desired VTRIP
Clock and Data Timing
Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. CS must be LOW during the entire operation.
Error -Emax
Error Emax
-Emax < Error < Emax DONE Emax = Maximum Desired Error FIGURE 4. VTRIP PROGRAMMING SEQUENCE
TABLE 1. INSTRUCTION SET INSTRUCTION NAME WREN WRDI RSDR WRSR READ WRITE Note: INSTRUCTION FORMAT* 0000 0110 0000 0100 0000 0101 0000 0001 0000 A8011 0000 A8010 OPERATION Set the Write Enable Latch (Enable Write Operations) Reset the Write Enable Latch (Disable Write Operations) Read Status Register Write Status Register (Watchdog and Block Lock) Read Data from Memory Array Beginning at Selected Address Write Data to Memory Array Beginning at Selected Address (1 to 16 bytes)
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
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Write Enable Latch
The device contains a Write Enable Latch. This latch must be SET before a Write Operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 5). This latch is automatically reset upon a power-up condition and after the completion of a valid byte, page, or status register write cycle. The latch is also reset if WP is brought LOW. When issuing a WREN, WRDI or RDSR commands, it is not necessary to send a byte address or data. the array that is block lock protected can be read but not written. It will remain protected until the BL bits are altered to disable block lock protection of that portion of memory.
STATUS REG BITS BL1 0 0 1 1 CS BL0 0 1 0 1 ARRAY ADDRESSES PROTECTED X5043, X5045 None $180-$1FF $100-$1FF $000-$1FF
0 SCK
1
2
3
4
5
6
7
The Watchdog Timer bits, WD0 and WD1, select the Watchdog Time-out Period. These nonvolatile bits are programmed with the WRSR instruction.
STATUS REGISTER BITS WD1 WD0 0 1 0 1 WATCHDOG TIME OUT (TYPICAL) 1.4 seconds 600 milliseconds 200 milliseconds disabled (factory default)
SI High Impedance
0 0
SO
1 1
FIGURE 5. WRITE ENABLE/DISABLE LATCH SEQUENCE (WREN/WRDI INSTRUCTION)
Read Status Register
To read the Status Register, pull CS low to select the device, then send the 8-bit RDSR instruction. Then the contents of the Status Register are shifted out on the SO line, clocked by CLK. Refer to the Read Status Register Sequence (Figure 6). The Status Register may be read at any time, even during a Write Cycle.
Status Register
The Status Register contains four nonvolatile control bits and two volatile status bits. The control bits set the operation of the watchdog timer and the memory block lock protection. The Status Register is formatted as shown in "Status Register".
Write Status Register
Prior to any attempt to write data into the status register, the "Write Enable" Latch (WEL) must be set by issuing the WREN instruction (Figure 5). First pull CS LOW, then clock the WREN instruction into the device and pull CS HIGH. Then bring CS LOW again and enter the WRSR instruction followed by 8 bits of data. These 8 bits of data correspond to the contents of the status register. The operation ends with CS going HIGH. If CS does not go HIGH between WREN and WRSR, the WRSR instruction is ignored.
Status Register: (Default = 30H)
7 0 6 0 5 WD1 4 WD0 3 BL1 2 BL0 1 WEL 0 WIP
The Write-In-Progress (WIP) bit is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. The WIP bit is read using the RDSR instruction. When set to a "1", a nonvolatile write operation is in progress. When set to a "0", no write is in progress. The Write Enable Latch (WEL) bit indicates the status of the "write enable" latch. When WEL = 1, the latch is set and when WEL = 0 the latch is reset. The WEL bit is a volatile, read only bit. The WREN instruction sets the WEL bit and the WRDS instruction resets the WEL bit. The block lock bits, BL0 and BL1, set the level of block lock protection. These nonvolatile bits are programmed using the WRSR instruction and allow the user to protect one quarter, one half, all or none of the EEPROM array. Any portion of
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TABLE 2. DEVICE PROTECT MATRIX WREN CMD (WEL) 0 x 1 MEMORY BLOCK DEVICE PIN (WP) x 0 1 PROTECTED AREA Protected Protected Protected UNPROTECTED AREA Protected Protected Writable STATUS REGISTER (BL0, BL1, WD0, WD1) Protected Protected Writable
CS
0 SCK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Instruction SI
SO
High Impedance
Data Out 7 MSB 6 5 4 3 2 1 0
FIGURE 6. READ STATUS REGISTER SEQUENCE
CS 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction SI 7 6 5
Data Byte 4 3 2 1 0
SO
High Impedance FIGURE 7. WRITE STATUS REGISTER SEQUENCE
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Read Memory Array
When reading from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 8-bit address. Bit 3 of the READ instruction selects the upper or lower half of the device. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address 000h allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS high. Refer to the Read EEPROM Array Sequence (Figure 8). For the write operation (byte or page write) to be completed, CS must be brought HIGH after bit 0 of the last complete data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 9). While the write is in progress following a status register or memory array write sequence, the Status Register may be read to check the WIP bit. WIP is HIGH while the nonvolatile write is in progress.
Write Memory Array
Prior to any attempt to write data into the memory array, the "Write Enable" Latch (WEL) must be set by issuing the WREN instruction (Figure 5). First pull CS LOW, then clock the WREN instruction into the device and pull CS HIGH. Then bring CS LOW again and enter the WRITE instruction followed by the 8-bit address and then the data to be written. Bit 3 of the WRITE instruction contains address bit A8, which selects the upper or lower half of the array. If CS does not go HIGH between WREN and WRITE, the WRITE instruction is ignored. The WRITE operation requires at least 16 clocks. CS must go low and remain low for the duration of the operation. The host may continue to write up to 16 bytes of data. The only restriction is that the 16 bytes must reside within the same page. A page address begins with address [x xxxx 0000] and ends with [x xxxx 1111]. If the byte address reaches the last byte on the page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that has been previously written.
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
12 13 14 15 16 17
18 19 20 21 22
Instruction SI 8 7 6
8 Bit Address 5 3 2 1 0
9th Bit of Address High Impedance SO 7 MSB FIGURE 8. READ EEPROM ARRAY SEQUENCE 6 5 4
Data Out 3 2 1 0
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CS 0 SCK Instruction SI 8 7 6 8 Bit Address 5 32 Data Byte 1 4321 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23
1
0
7
6
5
0
9th Bit of Address
CS 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK Data Byte 2 5432 Data Byte 3 5432 Data Byte N 4321
SI
7
6
1
0
7
6
1
0
6
5
0
FIGURE 9. WRITE MEMORY SEQUENCE
Operational Notes
The device powers-up in the following state: 1. The device is in the low power standby state. 2. A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. 3. SO pin is high impedance. 4. The Write Enable Latch is reset. 5. The Flag Bit is reset. 6. Reset Signal is active for tPURST.
Data Protection
The following circuitry has been included to prevent inadvertent writes: * A WREN instruction must be issued to set the Write Enable Latch. * CS must come HIGH at the proper clock count in order to start a nonvolatile write cycle. * Block Protect bits provide additional level of write protection for the memory array. * The WP pin LOW blocks nonvolatile write operations.
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Absolute Maximum Ratings
Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on any pin with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +7V D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . 300C
Recommended Operating Conditions
Temperature: Commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Supply Voltage: -2.7, -2.7A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Blank, -4.5A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Specifications
SYMBOL ICC1 ICC2 ISB1 ISB2 ILI ILO VIL
(1) (1)
(Over the recommended operating conditions unless otherwise specified.) LIMITS
PARAMETER VCC Write Current (Active) VCC Read Current (Active)
TEST CONDITIONS/COMMENTS SCK = 3.3MHz(3); SO, RESET, RESET = Open SCK = 3.3MHz(3); SI = VSS, RESET, RESET = Open
MIN
TYP(2)
MAX 3 2 10 50
UNIT mA mA A A A A V V V V V V
VCC Standby Current WDT = OFF CS = VCC, SCK, SI = VSS, VCC = 5.5V VCC Standby Current WDT = ON Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage (SO) Output HIGH Voltage (SO) Output HIGH Voltage (SO) Output HIGH Voltage (SO) Output LOW Voltage (RESET, RESET) CS = VCC, SCK, SI = VSS, VCC = 5.5V SCK, SI, WP = VSS to VCC SO, RESET, RESET = VSS to VCC SCK, SI, WP, CS SCK, SI, WP, CS IOL = 2mA @ VCC = 2.7V IOL = 0.5mA @ VCC = 1.8V VCC > 3.3V, IOH = -1.0mA 2V < VCC 3.3V, IOH = -0.4mA VCC 2V, IOH = -0.25mA IOL = 1mA VCC - 0.8 VCC - 0.4 VCC - 0.2 -0.5 VCC x 0.7 0.1 0.1
10 10 VCC x 0.3 VCC + 0.5 0.4
VIH
VOL VOH1 VOH2 VOH3 VOLRS
0.4
V
Capacitance
SYMBOL COUT CIN NOTES:
(2)
TA = +25C, f = 1MHz, VCC = 5V TEST CONDITIONS VOUT = 0V VIN = 0V MAX 8 6 UNIT pF pF
Output Capacitance (SO, RESET, RESET) Input Capacitance (SCK, SI, CS, WP)
(2)
1. VIL min. and VIH max. are for reference only and are not tested. 2. This parameter is periodically sampled and not 100% tested. 3. SCK frequency measured from VCC x 0.1/VCC x 0.9
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FN8126.1 September 16, 2005
X5043, X5045
Equivalent A.C. Load Circuit at 5V VCC
5V 5V 4.6k
A.C. Test Conditions
Input pulse levels Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5
1.64k Output 1.64k 30pF RESET/RESET
30pF
AC Electrical Specifications
SYMBOL DATA INPUT TIMING fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI(4) tFI(4) tCS tWC(5) Clock Frequency Cycle Time CS Lead Time CS Lag Time Clock HIGH Time Clock LOW Time Data Setup Time Data Hold Time Input Rise Time Input Fall Time CS Deselect Time Write Cycle Time
(Over recommended operating conditions, unless otherwise specified) 2.7V-5.5V PARAMETER MIN MAX UNIT
0 300 150 150 130 130 30 30
3.3
MHz ns ns ns ns ns ns ns
2 2 100 10
s s ns ms
Data Output Timing
2.7-5.5V SYMBOL fSCK tDIS tV tHO tRO tFO
(4)
PARAMETER Clock Frequency Output Disable Time Output Valid from Clock Low Output Hold Time Output Rise Time Output Fall Time
MIN 0
MAX 3.3 150 120
UNIT MHz ns ns ns
0 50 50
ns ns
(4)
NOTES: 4. This parameter is periodically sampled and not 100% tested. 5. tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
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FN8126.1 September 16, 2005
X5043, X5045
Serial Output Timing
CS tCYC SCK tV SO MSB Out MSB-1 Out tHO tWL LSB Out tDIS tWH tLAG
SI
ADDR LSB IN
Serial Input Timing
tCS CS tLEAD SCK tSU SI MSB In tH tRI
tFI
tLAG
LSB In
High Impedance SO
Symbol Table
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
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FN8126.1 September 16, 2005
X5043, X5045
Power-Up and Power-Down Timing
VCC VTRIP 0 Volts tR RESET (X5043) tPURST tPURST tF tRPD VTRIP
RESET (X5045)
RESET Output Timing
SYMBOL VTRIP PARAMETER Reset Trip Point Voltage, (-4.5A) Reset Trip Point Voltage, (Blank) Reset Trip Point Voltage, (-2.7A) Reset Trip Point Voltage, (-2.7) Power-up Reset Time Out VCC Detect to Reset/Output VCC Fall Time VCC Rise Time Reset Valid VCC 10 0.1 1 MIN 4.5 4.25 2.85 2.55 100 TYP 4.62 4.38 2.92 2.62 200 MAX 4.75 4.5 3.0 2.7 400 500 UNIT V
tPURST tRPD tF
(6)
ms ns s ns V
(6) (6)
tR
VRVALID NOTE:
6. This parameter is periodically sampled and not 100% tested.
CS/WDI vs. RESET/RESET Timing
CS/WDI tCST RESET (5043) tWDO RESET (5045) tRST tWDO tRST
RESET/RESET Output Timing
SYMBOL tWDO PARAMETER Watchdog Time Out Period, WD1 = 1, WD0 = 1 (default) WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 CS Pulse Width to Reset the Watchdog Reset Time Out MIN TYP OFF 200 600 1.4 MAX UNIT
100 450 1 400 100
300 800 2
ms ms sec ns
tCST tRST
200
400
ms
16
FN8126.1 September 16, 2005
X5043, X5045
VTRIP Programming Timing Diagram
VCC (VTRIP)
VTRIP tTSU VP tTHD
WP tVPS tVPH tVPO
tPCS
CS
tRP
SCK
SI 06h 02h 01h or 03h
VTRIP Programming Parameters
PARAMETER tVPS tVPH tPCS tTSU tTHD tWC tVPO tRP VP VTRAN Vtv DESCRIPTION VTRIP Program Enable Voltage Setup time VTRIP Program Enable Voltage Hold time VTRIP Programming CS inactive time VTRIP Setup time VTRIP Hold (stable) time VTRIP Write Cycle Time VTRIP Program Enable Voltage Off time (Between successive adjustments) VTRIP Program Recovery Period (Between successive adjustments) Programming Voltage VTRIP Programmed Voltage Range VTRIP Program variation after programming (0-75C). (Programmed at 25C.) 0 10 15 1.7 -25 18 4.75 +25 MIN 1 1 1 1 10 10 MAX UNIT s s s s ms ms s ms V V mV
VTRIP programming parameters are periodically sampled and are not 100% tested.
17
FN8126.1 September 16, 2005
X5043, X5045 Packaging Information
8-Lead Miniature Small Outline Gull Wing Package Type M
0.118 0.002 (3.00 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) Typ.
R 0.014 (0.36) 0.118 0.002 (3.00 0.05)
0.030 (0.76) 0.0216 (0.55)
0.036 (0.91) 0.032 (0.81)
7 Typ.
0.040 0.002 (1.02 0.05)
0.008 (0.20) 0.004 (0.10)
0.0256" Typical
0.007 (0.18) 0.005 (0.13)
0.150 (3.81) Ref. 0.193 (4.90) Ref.
0.025" Typical 0.220"
FOOTPRINT
0.020" Typical 8 Places
NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
18
FN8126.1 September 16, 2005
X5043, X5045 Packaging Information
8-Lead Plastic Dual In-Line Package Type P
0.430 (10.92) 0.360 (9.14)
0.260 (6.60) 0.240 (6.10) Pin 1 Index Pin 1 0.300 (7.62) Ref. 0.060 (1.52) 0.020 (0.51)
Half Shoulder Width On All End Pins Optional Seating Plane 0.150 (3.81) 0.125 (3.18)
0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.020 (0.51) 0.016 (0.41)
0.110 (2.79) 0.090 (2.29)
.073 (1.84) Max.
0.325 (8.25) 0.300 (7.62)
Typ. 0.010 (0.25)
0 15
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
19
FN8126.1 September 16, 2005
X5043, X5045 Packaging Information
8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1
0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7
0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25)
0.050 (1.27)
0.010 (0.25) X 45 0.020 (0.50)
0.050"Typical
0 - 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250"
0.050" Typical
FOOTPRINT
0.030" Typical 8 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
20
FN8126.1 September 16, 2005
X5043, X5045 Packaging Information
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.193 (4.9) .200 (5.1)
.047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05) See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 21
FN8126.1 September 16, 2005

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